1. Field of the Invention
This invention relates to semiconductor devices and, in particular, semiconductor devices employing large area oxides such as field oxides.
2. Art Background
In a variety of electronic devices, relatively large areas, e.g. 20 to 90 percent of the device surface area of dielectric material, are employed to isolate one device active region from another and/or to prevent electric fields in one region from adversely affecting active devices in another region. Examples of such large oxide regions are the field oxide in MOS technology as well as the field oxide isolation region in bipolar technology. In the former case, typical configurations are shown in FIG. 1, where 10 and 11 are the respective drains of field effect transistors 8 and 9, while 12 and 13 are the sources and 15 and 16 are the gates of these transistors.
Interconnection between gates must be configured so that the electrical conductors producing these connections do not adversely affect device operation and such that the operation of one field effect transistor does not adversely interfere with the operation of another. Typically, these desires are satisfied by a field oxide 17. This field oxide is usually thermally grown to a sufficient thickness-generally in the range 100 to 1000 nm--to prevent electric fields generated from runners that connect gates and junctions by traversing the region over the field oxide from producing a charge inverted region under the oxide. This inversion allows leakage currents to flow under the field oxide region between transistors. Similarly, in bipolar technology, a large oxide is employed typically for the same reason.
As design rules become stricter, i.e., as design rules decrease from 1 .mu.m to 0.6 .mu.m and finer, the large non-planarities associated with the large area dielectric regions produce significant processing difficulties. For example, a photoresist deposited on a non-planar surface generally assumes substantially the same contour as that surface. Thus, images focused on the photoresist, although in focus at one point on the resist surface, will be out of focus in the other regions of the resist surface that are not co-planar with the first. Thus, lithographic resolution is degraded.
Additionally, when etching a non-planar surface, further difficulties occur. As gate material in region 4 is etched and cleared, there remains a portion typically denominated a stringer, which must also be removed by further etching after the gate material has been removed from surfaces 20 and 21. However, this removal exposes surfaces 20 and 21 to further etching and therefore possible degradation. As a result, non-planarities for strict design rules are preferably avoided.
Attempts have been made to limit non-planarities introduced by large area dielectrics through the thinning of the dielectric, e.g. oxide, employed. These attempts have yielded unsatisfactory results. In particular, with thin dielectrics, such as thin field oxides, electric fields produced in the overlying electrical runners strongly affect the silicon underlying the oxide. The result of this interaction is two-fold. Capacitance increases which yields a decrease in device speed. Additionally, voltages through the runner must be limited so that the region 2 is not sufficiently inverted to produce substantial leakage currents, e.g., 10.sup.-7 to 10.sup.-9 amps between devices 8 and 9. Attempts to compensate for the effects of a thinned field oxide by increasing dopant levels in the substrate also lead to increased junction capacitance. As a result, although non-planarities associated with the field oxide cause undesirable effects, improvement has not been possible.